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Integrated Circuit Systems, Inc.
ICS93V857-XXX
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)
Recommended Application: * DDR Memory Modules / Zero Delay Board Fan Out * Provides complete DDR DIMM logic solution with ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852 Product Description/Features: * Low skew, low jitter PLL clock driver * 1 to 10 differential clock distribution (SSTL_2) * Feedback pins for input to output synchronization * PD# for power management * Spread Spectrum tolerant inputs * Auto PD when input signal removed * Choice of static phase offset available, for easy board tuning; -XXX = device pattern number for options listed below. - ICS93V857-025 ...... 0ps - ICS93V857-125 +125ps - ICS93V857-130 .. +40ps Switching Characteristics: * Period jitter (>66MHz): <40ps * CYCLE - CYCLE jitter (66MHz): <120ps * CYCLE - CYCLE jitter (>100MHz): <65ps * OUTPUT - OUTPUT skew: <60ps * Output Rise and Fall Time: 650ps - 950ps * DUTY CYCLE: 49.5% - 50.5%
Pin Configuration
GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD VDD CLK_INT CLK_INC VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PD# FB_INT FB_INC VDD FB_OUTC FB_OUTT GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP 4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
Block Diagram
FB_OUTT FB_OUTC CLKT0 CLKC0
ICS93V857-025/125/130
Functionality
Control
CLKT1 CLKC1
INPUTS AVDD PD# GND GND 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) H H L L H H X CLK_INT L H L H L H <20MHz)(1)
OUTPUTS PLL State CLK_INC CLKT CLKC FB_OUTT FB_OUTC H L H L H L L H Z Z L H Z H L Z Z H L Z L H Z Z L H Z H L Z Z H L Z Bypassed/off Bypassed/off off off on on off
PD#
Logic
CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4
FB_INT FB_INC CLK_INC CLK_INT
CLKT5 CLKC5
PLL
CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9
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ICS93V857-XXX
Pin Descriptions
PIN NUMBER 4, 11, 12, 15, 21, 28, 34, 38, 45, PIN NAME VDD TYPE PWR PWR PWR PWR OUT OUT IN IN OUT Power supply 2.5V Ground Analog power supply, 2.5V A n a l o g gr o u n d . "Tr ue" Clock of differential pair outputs. "Complementary" clocks of differential pair outputs. "Complementary" reference clock input "True" reference clock input "Complementary" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC. "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. "Complementary" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error. Power Down. LVCMOS input DESCRIPTION
1, 7, 8, 18, 24, 25, GND 31, 41, 42, 48 16 17 AVDD AGND
27, 29, 39, 44, 46, CLKT(9:0) 22, 20, 10, 5, 3 26, 30, 40, 43, 47, CLKC(9:0) 23, 19, 9, 6, 2 14 13 33 CLK_INC CLK_INT FB_OUTC
32 36 35 37
FB_OUTT FB_INT FB_INC PD#
OUT IN IN IN
This PLL Clock Buffer is designed for a VDD of 2.5V, AVDD of 2.5V and differential data input and output levels. ICS93V857-XXX is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT, FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD). When input (PD#) is low while power is applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INC, CLK_INT). The PLL in ICS93V857-XXX clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]). ICS93V857-XXX is also able to track Spread Spectrum Clock (SSC) for reduced EMI. ICS93V857-XXX is characterized for operation from 0C to 85C.
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ICS93V857-XXX
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V GND - 0.5V to VDD + 0.5V 0C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Input Clamp Voltage High-level output voltage Low-level output voltage SYMBOL I IH I IL IDD2.5 IDDPD VIK VOH VOL CONDITIONS VI = VDD or GND VI = VDD or GND CL = 0pf @ 100MHz CL = 0pf VDDQ = 2.3V Iin = -18mA IOH = -1 mA IOH = -12 mA IOL=1 mA IOL=12 mA VI = GND or V DD VOUT = GND or VDD MIN 5 TYP MAX 5 250 65 VDD - 0.1 1.7 2.45 2.10 0.05 0.35 3 3 90 -1.2 UNITS A A mA mA V V V V V pF pF
0.1 0.6
CIN Input Capacitance1 COUT Output Capacitance1 1 Guaranteed by design at 233MHz, not 100% tested in production.
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ICS93V857-XXX
Recommended Operating Condition (see note1)
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Supply Voltage Low level input voltage SYMBOL V DDQ, AVDD VIL CONDITIONS MIN 2.3 TYP 2.5 0.4 MAX 2.7 V DD/2 - 0.18 0.7 2.1 V DD + 0.6 V DD + 0.3 V DD + 0.6 V DD + 0.6 VDD/2 + 0.15 VDD/2 VDD/2 + 0.2 -12 12 VDD=2.7V, VOUT=VDD or GND 0 0.1 10 85 UNITS V V V V V V V V V V mA mA mA C
High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current Low level output current High Impedance Output Current Operating free-air temperature
VIH VIN
CLK_INT, CLK_INC, FB_INC, FB_INT PD# -0.3 CLK_INT, CLK_INC, FB_INC, VDD/2 + 0.18 FB_INT PD# 1.7 -0.3 DC - CLK_INT, CLK_INC, FB_INC, FB_INT AC - CLK_INT, CLK_INC, FB_INC, FB_INT 0.36 0.7 VDD/2 - 0.15 V DD/2 - 0.2
VID
V OX VIX IOH IOL IOZ TA
Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing.
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ICS93V857-XXX
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX Max clock frequency Application Frequency Range3 Input clock duty cycle CLK stabilization
3
UNITS MHz MHz % s
freqop freqApp dtin TSTAB
2.5V+0.2V 2.5V+0.2V
33 60 40
233 170 60 100
Switching Characteristics
PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Input clock slew rate Output clock slew rate Cycle to Cycle Jitter1 Phase error Output to Output Skew Rise Time, Fall Time SYMBOL tPLH1 tPHL1 ten tdis tjit (per) tjit(hper) t sl(I) t sl(o) tcyc -tcyc t(phase error)4 t skew t r, t f CONDITION CLK_IN to any output CLK_IN to any output PD# to any output PD# to any output 66/100/125/133/167MHz 100 to <170MHz 170MHz to 233MHz 66/100/133/167MHz 66/100/125/133/167MHz MIN TYP 5.5 5.5 5 5 -40 -100 -120 1 1 -50 Load = 120/16pF 650 0 40 800 40 100 50 4 2 60 50 60 950 MAX UNITS ns ns ns ns ps ps ps v/ns v/ns ps ps ps ps
Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design.
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ICS93V857-XXX
Parameter Measurement Information VDD V(CLKC)
R = 60
R = 60 VDD /2 V(CLKC) ICS93V857 GND Figure 1. IBIS Model Output Load VDD/2 ICS93V857 Z = 60 C = 14 pF -VDD/2 R = 10 Z = 50 SCOPE
R = 50 V(TT) Z = 60 R = 10 Z = 50
C = 14 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit
R = 50 V(TT)
YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) tc(n+1) Figure 3. Cycle-to-Cycle Jitter
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ICS93V857-XXX
Parameter Measurement Information CLK_INC CLK_INT
FB_INC FB_INT
t( ) n
n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX# YX
YX, FB_OUTC YX, FB_OUTT t(skew) Figure 5. Output Skew
YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT
tC(n)
1 fO t(jit_per) = tc(n) - 1 fO Figure 6. Period Jitter
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ICS93V857-XXX
Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT
t jit(hper_n) 1 fo t jit(hper_n+1)
tjit(hper) = t jit(hper_n)
-
1 2xfO
Figure 7. Half-Period Jitter
80%
80% VID, VOD
Clock Inputs and Outputs
20% tslr tslf
20%
Figure 8. Input and Output Slew Rates
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ICS93V857-XXX
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS
-Ce
b SEATING PLANE
N 48
10-0039
D mm. MIN MAX 12.40 12.60
D (inch) MIN .488 MAX .496
aaa C
Reference Doc.: JEDEC Publication 95, M O-153
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
Choice of static phase offset available, for easy board tuning; -XXX = device pattern number for options listed below. - ICS93V857-025 ...... 0ps - ICS93V857-125 +125ps - ICS93V857-130 .. +40ps
Ordering Information
ICS93V857yG-025T ICS93V857yG-125T ICS93V857yG-130T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS = Standard Device
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ICS93V857-XXX
N
c
L
SYMBOL A A1 A2 b c D E E1 e L N aaa
INDEX AREA
E1
E
12 D
A2 A1
A
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.13 0.23 .005 .009 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 6.40 BASIC 0.252 BASIC 4.30 4.50 .169 .177 0.40 BASIC 0.016 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 -0.08 -.003
VARIATIONS
-C-
N 48
10-0037
D mm. MIN 9.60 MAX 9.80 MIN .378
D (inch) MAX .386
e
b
SEATING PLANE
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
4.40 mm. Body, 0.40 mm. pitch TSSOP (173 mil) (16 mil)
Choice of static phase offset available, for easy board tuning; -XXX = device pattern number for options listed below. - ICS93V857-025 ...... 0ps - ICS93V857-125 +125ps - ICS93V857-130 .. +40ps
Ordering Information
ICS93V857yL-025T ICS93V857yL-125T ICS93V857yL-130T
Example:
ICS XXXX y L - PPP - T
Designation for tape and reel packaging Pattern Number Package Type L=TSSOP (TVSOP)
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS = Standard Device
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